PRJ-04 · UCSC CSE 100

Lab 6: FPGA VGA Game Logic

Outcome: Designed and implemented a complete VGA based game in Verilog on the Basys3 FPGA, combining raster graphics, player input, randomized object behavior, collision detection, and hardware outputs. The project required careful coordination of display timing, pixel level rendering, and synchronous game logic within a single FPGA design.

Placeholder: FPGA board running lab 6
Fig. 1 — Lab 6 running on the Basys3 FPGA with VGA output displaying the complete game screen.

What I Did

  • Implemented VGA timing and coordinate based rendering logic in Verilog for the background, tree, player, and falling apples.
  • Developed synchronous game logic for button controlled player movement, collision detection, randomized apple behavior, and LED based life tracking.
  • Added extra credit behavior including a faster golden apple that awarded an additional life and pre fall apple movement.

Motivation

Lab 6 combined the digital design concepts developed throughout CSE 100 into a single FPGA system. The goal was to generate a complete interactive VGA display directly from Verilog while coordinating user inputs, hardware outputs, graphical objects, and game state. A major challenge was managing pixel coordinates and drawing priority so independently generated objects appeared in the correct locations without incorrectly overwriting one another.

Results

The completed FPGA design generated the full game display on a VGA monitor, accepted push button input to move the player, tracked lives through the Basys3 LEDs, and detected collisions with falling apples. The design also implemented the extra credit golden apple behavior and apple movement before falling.

Technical Details

The design used Verilog to generate VGA output from the Basys3 FPGA using screen coordinates to determine the color of each displayed pixel. Separate logic controlled the background, tree, player, and falling objects, requiring explicit rendering priority when multiple objects occupied overlapping regions. Sequential logic handled player movement, object position updates, randomized apple behavior, collision detection, and life tracking. The design was developed using Icarus Verilog for simulation, Yosys for structural checks, and openFPGALoader for deployment to the FPGA.

Role
Individual lab
Timeline
CSE 100 Lab 6
Context
UCSC CSE 100 (Logic Design)
Tools
Verilog, Icarus Verilog, Yosys, openFPGALoader, Basys3 FPGA
Skills
RTL design · VGA graphics · Synchronous logic · Hardware verification
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